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piel.tools.cocotb.core

piel.tools.cocotb.core#

The objective of this file is to provide the simulation ports and interconnection to consider modelling digital and mixed signal logic.

The main simulation driver is cocotb, and this generates a set of files that correspond to time-domain digital simulations. The cocotb verification software can also be used to perform mixed signal simulation, and digital data can be inputted as a bitstream into a photonic solver, although the ideal situation would be to have integrated photonic time-domain models alongside the electronic simulation solver, and maybe this is where it will go. It can be assumed that, as is currently, cocotb can interface python with multiple solvers until someone (and I’d love to do this) writes an equivalent python-based or C++ based python time-domain simulation solver.

The nice thing about cocotb is that as long as the photonic simulations can be written asynchronously, time-domain simulations can be closely integrated or simulated through this verification software.

Module Contents#

Functions#

check_cocotb_testbench_exists(→ bool)

Checks if a cocotb testbench exists in the design directory.

configure_cocotb_simulation(design_directory, ...[, ...])

Writes a cocotb makefile.

run_cocotb_simulation(→ subprocess.CompletedProcess)

Equivalent to running the cocotb makefile

Attributes#

delete_simulation_output_files

check_cocotb_testbench_exists(design_directory: str | pathlib.Path) → bool[source]#

Checks if a cocotb testbench exists in the design directory.

Parameters:

design_directory (str | pathlib.Path) – Design directory.

Returns:

True if cocotb testbench exists.

Return type:

cocotb_testbench_exists(bool)

configure_cocotb_simulation(design_directory: str | pathlib.Path, simulator: Literal[icarus, verilator], top_level_language: Literal[verilog, vhdl], top_level_verilog_module: str, test_python_module: str, design_sources_list: list | None = None)[source]#

Writes a cocotb makefile.

If no design_sources_list is provided then it adds all the design sources under the src folder.

In the form .. code-block:

#!/bin/sh
# Makefile
# defaults
SIM ?= icarus
TOPLEVEL_LANG ?= verilog

# Note we need to include the test script to the PYTHONPATH
export PYTHONPATH =

VERILOG_SOURCES += $(PWD)/my_design.sv
# use VHDL_SOURCES for VHDL files

# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL := my_design

# MODULE is the basename of the Python test file
MODULE := test_my_design

# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim
Parameters:

  • design_directory (str | pathlib.Path) – The directory where the design is located.

  • simulator (Literal["icarus", "verilator"]) – The simulator to use.

  • top_level_language (Literal["verilog", "vhdl"]) – The top level language.

  • top_level_verilog_module (str) – The top level verilog module.

  • test_python_module (str) – The test python module.

  • design_sources_list (list | None, optional) – A list of design sources. Defaults to None.

Returns:

None

delete_simulation_output_files#
run_cocotb_simulation(design_directory: str) → subprocess.CompletedProcess[source]#

Equivalent to running the cocotb makefile .. code-block:

make
Parameters:

design_directory (str) – The directory where the design is located.

Returns:

The subprocess.CompletedProcess object.

Return type:

subprocess.CompletedProcess

Contents