piel.tools.amaranth
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Submodules#
Package Contents#
Functions#
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This function implements a truth table as a module in amaranth, |
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This function exports an amaranth module to either a defined path, or a project structure in the form of an |
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We will implement a function that tests the module to verify that the outputs generates match the truth table provided. |
- construct_amaranth_module_from_truth_table(truth_table: dict, inputs: list[str], outputs: list[str], implementation_type: Literal[combinatorial, sequential, memory] = 'combinatorial')[source]#
This function implements a truth table as a module in amaranth, Note that in some form in amaranth each statement is a form of construction.
The truth table is in the form of:
- detector_phase_truth_table = {
“detector_in”: [“00”, “01”, “10”, “11”], “phase_map_out”: [“00”, “10”, “11”, “11”],
}
- Parameters:
truth_table (dict) – The truth table in the form of a dictionary.
inputs (list[str]) – The inputs to the truth table.
outputs (list[str]) – The outputs to the truth table.
implementation_type (Literal["combinatorial", "sequential", "memory"], optional) – The type of implementation. Defaults to “combinatorial”.
- Returns:
Generated amaranth module.
- generate_verilog_from_amaranth(amaranth_module: amaranth.Elaboratable, ports_list: list[str], target_file_name: str, target_directory: piel.types.piel_path_types, backend=verilog) None [source]#
This function exports an amaranth module to either a defined path, or a project structure in the form of an imported multi-design module.
Iterate over ports list and construct a list of references for the strings provided in
ports_list
- Parameters:
amaranth_module (amaranth.Elaboratable) – Amaranth elaboratable class.
ports_list (list[str]) – List of input names.
target_file_name (str) – Target file name.
target_directory (piel_path_types) – Target directory PATH.
backend (amaranth.back.verilog) – Backend to use. Defaults to
verilog
.
- Returns:
None
- verify_truth_table(truth_table_amaranth_module: amaranth.Elaboratable, truth_table_dictionary: dict, inputs: list, outputs: list, vcd_file_name: str, target_directory: piel.types.piel_path_types, implementation_type: Literal[combinatorial, sequential, memory] = 'combinatorial')[source]#
We will implement a function that tests the module to verify that the outputs generates match the truth table provided.
TODO Implement a similar function from the openlane netlist too. TODO unclear they can implement verification without it being in a synchronous simulation.