piel.types.digital

piel.types.digital#

This module defines files measurement and measurement for working with digital circuits and logic signals. It leverages pydantic for model validation and pandas for files manipulation.

Attributes#

`AbstractBitsType`	Alias for measurement representing digital bits.
`BitsType`	A type representing binary digital bits.
`BitsList`	An iterable collection of AbstractBitsType elements.
`DigitalRunID`
`HDLSimulator`	A literal type representing supported HDL simulators.
`HDLTopLevelLanguage`	A literal type representing top-level hardware description languages.
`LogicSignalsList`	A list of strings representing the names of logic signals.
`TruthTableLogicType`
`LogicImplementationType`
`DigitalLogicModule`

Classes#

TruthTable

A model representing a truth table for a digital circuit, including its input and output connection.

Module Contents#

AbstractBitsType#

Alias for measurement representing digital bits. Can be one of: - str: A string representation of bits. - bytes: A byte representation of bits. - int: An integer representation of bits.

Type:: AbstractBitsType

BitsType#

A type representing binary digital bits. It is an alias for the ‘str’ type.

Type:: BitsType

BitsList#

An iterable collection of AbstractBitsType elements. Represents a sequence of digital bits.

Type:: BitsList

DigitalRunID#

HDLSimulator#

A literal type representing supported HDL simulators. Can be one of: - “icarus”: Refers to Icarus Verilog simulator. - “verilator”: Refers to Verilator simulator.

Type:: HDLSimulator

HDLTopLevelLanguage#

A literal type representing top-level hardware description languages. Can be one of: - “verilog”: Refers to the Verilog HDL. - “vhdl”: Refers to the VHDL HDL.

Type:: HDLTopLevelLanguage

LogicSignalsList#

A list of strings representing the names of logic signals.

Type:: LogicSignalsList

TruthTableLogicType#

LogicImplementationType#

class TruthTable(/, **data: Any)[source]#

Bases: piel.types.core.PielBaseModel

A model representing a truth table for a digital circuit, including its input and output connection.

input_ports#

List of input signal names for the truth table.

Type:: LogicSignalsList

output_ports#

List of output signal names for the truth table.

Type:: LogicSignalsList

Properties:: keys_list (list[str]): A combined list of input and output signal names. dataframe (pd.DataFrame): A pandas DataFrame representation of the truth table, excluding input and output connection. implementation_dictionary (dict): A dictionary including only the keys specified within input_ports and output_ports.

model_config#: Configuration for the model, should be a dictionary conforming to [ConfigDict][pydantic.config.ConfigDict].

input_ports: LogicSignalsList#

List of input signal names for the truth table.

Type:: input_ports (LogicSignalsList)

output_ports: LogicSignalsList#

List of output signal names for the truth table.

Type:: output_ports (LogicSignalsList)

property ports_list: list[str]#

Returns a combined list of input and output signal names.

Returns:: The concatenated list of input and output connection.
Return type:: list[str]

property dataframe: pandas.DataFrame#

Returns a pandas DataFrame representation of the truth table, excluding the input and output connection.

Returns:: A DataFrame with the truth table files, excluding input and output port keys.
Return type:: pd.DataFrame

property implementation_dictionary: dict#

Returns a dictionary including only the keys specified within input_ports and output_ports.

Returns:: A dictionary with keys that are part of the input and output connection.
Return type:: dict

DigitalLogicModule#