piel.tools.amaranth

piel.tools.amaranth#

Submodules#

Functions#

construct_amaranth_module_from_truth_table(truth_table)

Constructs an Amaranth module based on the provided truth table.

generate_verilog_from_amaranth_truth_table(→ None)

Exports an Amaranth module to Verilog code and writes it to a specified path.

verify_amaranth_truth_table(...[, implementation_type])

Verifies that the outputs generated by the given Amaranth module match the provided truth table.

Package Contents#

construct_amaranth_module_from_truth_table(truth_table: piel.types.digital.TruthTable, logic_implementation_type: piel.types.digital.LogicImplementationType = 'combinatorial')[source]#

Constructs an Amaranth module based on the provided truth table. # TODO implementation type

Parameters:

  • truth_table (TruthTable) – The truth table to be implemented as a TruthTable object.

  • logic_implementation_type (Literal["combinatorial", "sequential", "memory"], optional) – The type of implementation. - “combinatorial”: Implements the truth table as combinational logic. - “sequential”: Implements the truth table as sequential logic. - “memory”: Implements the truth table using memory elements. Defaults to “combinatorial”.

Returns:

An Amaranth module implementing the given truth table.

Return type:

am.Module

Examples

>>> detector_phase_truth_table = {
>>>     "detector_in": ["00", "01", "10", "11"],
>>>     "phase_map_out": ["00", "10", "11", "11"],
>>> }
>>> my_truth_table = TruthTable(
>>>     input_ports=["detector_in"],
>>>     output_ports=["phase_map_out"],
>>>     **detector_phase_truth_table
>>> )
>>> am_module = construct_amaranth_module_from_truth_table(my_truth_table)
generate_verilog_from_amaranth_truth_table(amaranth_module: Any, truth_table: piel.types.TruthTable, target_file_name: str, target_directory: piel.types.PathTypes, backend: Literal['verilog', 'vhdl'] = 'verilog') → None[source]#

Exports an Amaranth module to Verilog code and writes it to a specified path.

This function converts an Amaranth elaboratable class to Verilog using the specified backend and writes the generated code to a file in the target directory. It supports both direct paths and paths defined by the project’s module structure.

Parameters:

  • amaranth_module (amaranth.Elaboratable) – The Amaranth module to be converted.

  • truth_table (TruthTable) – A truth table object containing input and output connection.

  • target_file_name (str) – The name of the target file to write the Verilog code to.

  • target_directory (PathTypes) – The target directory where the file will be saved. Can be a direct path or a module type path.

  • backend (amaranth.back.verilog, optional) – The backend to use for Verilog conversion. Defaults to verilog.

Returns:

None

Raises:

AttributeError – If any port specified in the truth table is not found in the Amaranth module.

Examples

>>> am_module = MyAmaranthModule()  # Assuming this is a defined Amaranth module.
>>> truth_table = TruthTable(
>>>     input_ports=["input1", "input2"],
>>>     output_ports=["output1"],
>>>     input1=["00", "01", "10", "11"],
>>>     output1=["0", "1", "1", "0"]
>>> )
>>> generate_verilog_from_amaranth_truth_table(am_module, truth_table, "output.v", "/path/to/save")
verify_amaranth_truth_table(truth_table_amaranth_module: Any, truth_table: piel.types.digital.TruthTable, vcd_file_name: str, target_directory: piel.types.PathTypes, implementation_type: Literal['combinatorial', 'sequential', 'memory'] = 'combinatorial')[source]#

Verifies that the outputs generated by the given Amaranth module match the provided truth table.

This function runs a simulation of the Amaranth module and checks if the outputs for each set of inputs match the expected outputs as specified in the truth table. It can optionally generate a VCD file for detailed analysis.

Parameters:

  • truth_table_amaranth_module (amaranth.Elaboratable) – The Amaranth module to be verified.

  • truth_table (TruthTable) – The truth table specifying expected inputs and outputs.

  • vcd_file_name (str) – The name of the VCD file to generate for the simulation.

  • target_directory (PathTypes) – The directory where the VCD file will be saved. Can be a direct path or a module type path.

  • implementation_type (Literal["combinatorial", "sequential", "memory"], optional) – The type of implementation to simulate. Defaults to “combinatorial”.

Returns:

None

Raises:

AttributeError – If the specified connection are not found in the Amaranth module.

Examples

>>> am_module = MyAmaranthModule()  # Assuming this is a defined Amaranth module.
>>> truth_table = TruthTable(
>>>     input_ports=["input1"],
>>>     output_ports=["output1", "output2"],
>>>     input1=["0", "1"],
>>>     output1=["1", "0"],
>>>     output2=["0", "1"]
>>> )
>>> verify_amaranth_truth_table(am_module, truth_table, "output.vcd", "/path/to/save")
Contents