piel.tools.amaranth.export
==========================

.. py:module:: piel.tools.amaranth.export

.. autoapi-nested-parse::

   This module provides a utility to generate Verilog code from an Amaranth module based on a given truth table.
   It handles the conversion and export process, integrating with a specified file system structure.



Functions
---------

.. autoapisummary::

   piel.tools.amaranth.export.generate_verilog_from_amaranth_truth_table


Module Contents
---------------

.. py:function:: generate_verilog_from_amaranth_truth_table(amaranth_module: Any, truth_table: piel.types.TruthTable, target_file_name: str, target_directory: piel.types.PathTypes, backend: Literal['verilog', 'vhdl'] = 'verilog') -> None

   Exports an Amaranth module to Verilog code and writes it to a specified path.

   This function converts an Amaranth elaboratable class to Verilog using the specified backend
   and writes the generated code to a file in the target directory. It supports both direct paths
   and paths defined by the project's module structure.

   :param amaranth_module: The Amaranth module to be converted.
   :type amaranth_module: amaranth.Elaboratable
   :param truth_table: A truth table object containing input and output connection.
   :type truth_table: TruthTable
   :param target_file_name: The name of the target file to write the Verilog code to.
   :type target_file_name: str
   :param target_directory: The target directory where the file will be saved.
                            Can be a direct path or a module type path.
   :type target_directory: PathTypes
   :param backend: The backend to use for Verilog conversion. Defaults to `verilog`.
   :type backend: amaranth.back.verilog, optional

   :returns: None

   :raises AttributeError: If any port specified in the truth table is not found in the Amaranth module.

   .. rubric:: Examples

   >>> am_module = MyAmaranthModule()  # Assuming this is a defined Amaranth module.
   >>> truth_table = TruthTable(
   >>>     input_ports=["input1", "input2"],
   >>>     output_ports=["output1"],
   >>>     input1=["00", "01", "10", "11"],
   >>>     output1=["0", "1", "1", "0"]
   >>> )
   >>> generate_verilog_from_amaranth_truth_table(am_module, truth_table, "output.v", "/path/to/save")